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| information furnished by analog devices is be lieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or oth- erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. t el: 781/329-4700 www.analog.com fa x: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. adp3180 * 6-bit programmable 2-, 3-, 4-phase synchronous buck controller * pa tent pending features selectable 2-, 3-, or 4-phase operation at up to 1 mhz per phase 14.5 mv worst-case differential sensing error over te m perature logic-level pwm outputs for interface to external high power drivers ac tive current balancing between all output phases built-in power good/crowbar blanking supports on-the-fly vid code changes 6-bit digitally programmable 0.8375 v to 1.6 v output programmable short circuit protection with programmable latch-off delay applications desktop pc power supplies for: next generation intel ? processors vrm modules functional block diagram pwm2 fb pwm3 pwm4 sw1 cssum cscomp sw2 sw3 sw4 csref pwm1 adp3180 vid4 vid3 vid2 vid1 vid5 vid0 fbrtn gnd en delay ilimit pwrgd comp vcc rt rampadj crowbar current limit 2-, 3-, 4-phase driver logic en set reset reset reset reset oscillator cmp cmp cmp cmp current ba lancing circuit delay uvlo shutdown and bias dac +150mv dac ?250mv csref precision reference soft- start vid dac en current limit circuit 19 11 12 15 10 28 13 14 26 8 25 24 23 17 18 22 21 20 16 1234 6 5 7 9 27 general description the adp3180 is a highly ef cient multiphase synchronous buck s witching regulator controller optimized for converting a 12 v main supply into the core supply voltage required by high per- formance intel processors. it uses an internal 6-bit dac to read a voltage identi cation (vid) code directly from the processor, which is used to set the output voltage between 0.8375 v and 1.6 v, and uses a multimode pwm architecture to drive the logic level outputs at a programmable switching frequency that can be optimized for vr size and ef ciency. the phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four comple- mentary buck switching stages. the adp3180 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. the adp3180 also provides accurate and reliable short circuit protection, adjustable current limiting, and a delayed po w er good output that accommodates on-the- y output voltage changes requested by the cpu. adp3180 is speci ed over the commercial temperature range of 0? to 85? and is available in a 28-lead tssop package. rev. 0
?2? adp3180?specifications 1 (vcc = 12 v, fbrtn = gnd, t a = 0 c to 85 c, unless otherwise noted.) p arameter symbol conditions min typ max unit error amplifier output voltage range accuracy line regulation input bias current fbrtn current output current gain bandwidth product slew rate v comp v fb d () w () d , , = ( ) = = = . . . . . +. d , , d d d d (d) (d) (d) (d) d d() = d() = . d d w . . . . w d d d d = , = w , = , = w , = , = w , = w d d . . . . + () () w () d , = = . + + . w() w() w() d w() w() = w() = w() = + + w , d d d () (d) () d() d() d . , = w . , = . , = w . , = w d = w , d = . . . . . . . . . (). , . . . adp3180 ?3? p arameter symbol conditions min typ max unit soft start output current, soft-start mode soft-start delay time i delay(ss) t delay(ss) during startup, delay < 2.8 v r delay = 250 k w , d = . d = , , () () () () = = . . . + w d d d d d d d wd() wd() (wd) w w d d wd() = d w + + + + + w (w) (w) w() = w() = . . d . . . . . . . . adp3180 ?4? pin configuration adp3180 top view (not to scale) vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 1 2 3 28 27 26 4 8 10 12 14 5 6 7 21 24 23 22 9 11 17 18 19 13 15 16 20 25 absolute maximum ratings * vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +15 v fbrtn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v vid0evid5, en, delay, ilimit, cscomp, rt, pwm1epwm4, comp . . . . . . . . . . . . . . . . e0.3 v to +5.5 v sw1esw4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e5 v to +25 v all other inputs and outputs . . . . . . . . . e0.3 v to vcc + 0.3 v operating ambient temperature range . . . . . . . . 0?c to 85?c operating junction temperature . . . . . . . . . . . . . . . . . . . 125?c storage temperature range . . . . . . . . . . . . . . e65?c to +150?c junction to air thermal resistance ( ja ) . . . . . . . . . . . 100?c/w lead temperature (soldering, 10 sec) . . . . . . . . . . . . . . . 300?c v apor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215?c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220?c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specit cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specit ed, all other voltages are referenced to gnd. ordering guide model t emperature range pa ckage options quantity per reel adp3180jru-reel7 adp3180jru-reel 0?c to 85?c 0?c to 85?c ru-28 (tssop-28) ru-28 (tssop-28) 1000 2500 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily ac cu mu late on the human body and test equipment and can discharge without detection. although the adp3180 features proprietary esd pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. rev. 0 adp3180 ?5? pin function descriptions pin no. mnemonic function 1e6 vid4evid0, vid5 v oltage identit cation dac inputs. these six pins are pulled up to an internal reference, providing a logic one if left open. when in normal operation mode, the dac output programs the fb regulation voltage from 0.8375 v to 1.6 v. leaving vid4 through vid0 open results in the adp3180 going into a no cpu mode, shutting off its pwm outputs. 7 fbrtn feedback return. vid dac and error amplit er reference for remote sensing of the output voltage. 8f bf eedback input. error amplit er input for remote sensing of the output voltage. an external resistor between this pin and the output voltage sets the no-load offset point. 9 comp error amplit er output and compensation point 10 pwrgd power good output. open-drain output that pulls to gnd when the output voltage is outside of the proper operating range. 11 en power supply enable input. pulling this pin to gnd disables the pwm outputs. 12 delay soft-start delay and current limit latch-off delay setting input. an external resistor and capacitor connected between this pin and gnd set the soft-start ramp-up time and the overcurrent latch-off delay time. 13 rt frequency setting resistor input. an external resistor connected between this pin and gnd sets the oscillator frequency of the device. 14 rampadj pwm ramp current input. an external resistor from the converter input voltage to this pin sets the internal pwm ramp. 15 ilimit curr ent limit set point/enable output. an external resistor from this pin to gnd sets the current limit threshold of the converter. this pin is actively pulled low when the adp3180 en input is low or when vcc is below its uvlo threshold to signal to the driver ic that the driver high side and low side outputs should go low. 16 csref current sense reference voltage input. the voltage on this pin is used as the reference for the current sense amplit er and the power good and crowbar functions. this pin should be connected to the common point of the output inductors. 17 cssum current sense summing node. external resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 18 cscomp current sense compensation point. a resistor and capacitor from this pin to cssum determine the slope of the load line and the positioning loop response time. 19 gnd ground. all internal biasing and the logic output signals of the device are referenced to this ground. 20e23 sw4esw1 current balance inputs. inputs for measuring the current level in each phase. the sw pins of unused phases should be left open. 24e27 pwm4e pwm1 logic-level pwm outputs. each output is connected to the input of an external mosfet driver, such as the adp3413 or adp3418. connecting the pwm3 and/or pwm4 outputs to gnd will cause that phase to turn off, allowing the adp3180 to operate as a 2-, 3-, or 4-phase controller. 28 vcc supply voltage for the device. rev. 0 ?6? adp3180?typical performance characteristics 4 3 2 1 0 master clock frequency ? mhz r t val ue ? k see equation 1 for frequencies not on this graph 0 50 100 150 200 250 300 tpc 1. master clock frequency vs. r t test circuits cssum 18 cscomp 17 28 vcc csref 16 gnd 19 39k 100nf 1k 1.0v adp3180 12v v os = cscomp ? 1v 40 t est circuit 1. current sense ampli er v os cssum 18 cscomp 17 28 vcc csref 16 comp 8 fb 9 gnd 19 200k 10k 200k 1.0v adp3180 v 12v 100nf v fb = fb v = 80mv ? fb v = 0mv t est circuit 2. positioning voltage 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 supply current ? ma master clock frequency ? mhz t a = 25 c 4-phase operation tpc 2. supply current vs. master clock frequency + 250k 12v 1 f 100nf 100nf vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 28 27 26 21 24 23 22 17 18 19 15 16 20 25 20k adp3180 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj 1 2 3 4 8 10 12 14 5 6 7 9 11 13 1.25v 6-bit code 250k 1k 4.7nf t est circuit 3. closed-loop output voltage accuracy rev. 0 adp3180 ?7? vid4 vid3 vid2 vid1 vid0 vid5 v out(nom) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 no cpu 0.8375 v 0.850 v 0.8625 v 0.875 v 0.8875 v 0.900 v 0.9125 v 0.925 v 0.9375 v 0.950 v 0.9625 v 0.975 v 0.9875 v 1.000 v 1.0125 v 1.025 v 1.0375 v 1.050 v 1.0625 v 1.075 v 1.0875 v 1.100 v 1.1125 v 1.125 v 1.1375 v 1.150 v 1.1625 v 1.175 v 1.1875 v 1.200 v 1.2125 v vid4 vid3 vid2 vid1 vid0 vid5 v out(nom) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.225 v 1.2375 v 1.250 v 1.2625 v 1.275 v 1.2875 v 1.300 v 1.3125 v 1.325 v 1.3375 v 1.350 v 1.3625 v 1.375 v 1.3875 v 1.400 v 1.4125 v 1.425 v 1.4375 v 1.450 v 1.4625 v 1.475 v 1.4875 v 1.500 v 1.5125 v 1.525 v 1.5375 v 1.550 v 1.5625 v 1.575 v 1.5875 v 1.600 v x = don't care ta b le i. output voltage vs. vid code theory of operation the adp3180 combines a multimode, t x ed frequency pwm control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck cpu core supply power converters. the internal 6-bit vid dac conforms to intel?s vrd/vrm 10 specit cations. multiphase operation is important for produc- ing the high currents and low voltages demanded by today?s microprocessors. handling the high currents in a single-phase converter would place high thermal demands on the components in the system such as the inductors and mosfets. the multimode control of the adp3180 ensures a stable, high performance topology for: w . , d w . w , w w . w d , w w . . , . w w . w w . . , w , w . w , . . adp3180 ?8? the pwm outputs become logic-level devices once normal operation starts. the detection is normal and is intended for driv- ing external gate drivers, such as the adp3418. since each phase is monitored independently, operation approaching 100% duty c ycle is possible. also, more than one output can be on at a time for overlapping phases. master clock frequency the clock frequency of the adp3180 is set with an external resistor connected from the rt pin to ground. the frequency fol- lows the graph in tpc 1. to determine the frequency per phase, the clock is divided by the number of phases in use. if pwm4 is g rounded, divide the master clock by 3 for the frequency of the remaining phases. if pwm3 and pwm4 are grounded, divide by 2. if all phases are in use, divide by 4. output voltage differential sensing the adp3180 combines differential sensing with a high accuracy vid dac and reference and a low offset error amplit er to main- tain a worst-case specit cation of 10 mv differential sensing error with a vid input of 1.6000 v over its full operating output v oltage and temperature range. the output voltage is sensed between the fb and fbrtn pins. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 90 a to allow accurate remote sensing. the internal error amplit er compares the output of the dac to the fb pin to regu- late the output voltage. output current sensing the adp3180 provides a dedicated current sense amplit er (csa) to monitor the total output current for proper voltage positioning versus load current and for current limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low side mosfet. this amplit er can be cont gured several ways, depending on the objectives of the system: , . ( ) , . , . . . d d . , . , . , . . d . . d . . . . . d w . d . , . w w ( ) . , . , w ( w = ). w w . w , . . d . , . , w . () . d . d d. . d . . . adp3180 ?9? en is a logic low, the delay pin is held at ground. after the uvlo threshold is reached and en is a logic high, the delay capacitor is charged up with an internal 20 a current source. the output voltage follows the ramping voltage on the delay pin, limiting the inrush current. the soft-start time depends on the values of vid dac and c dly , with a secondary effect from r dly . refer to the application information section for detailed information on setting c dly . when the pwrgd threshold is reached, the soft-start cycle is stopped and the delay pin is pulled up to 3 v. this ensures that the output voltage is at the vid voltage when the pwrgd signals to the system that the output voltage is good. if en is taken low or vcc drops below uvlo, the delay capacitor is reset to ground to be ready for another soft-start cycle. figure 1 shows a typical start-up sequence for the adp3180. figure 1. start-up waveforms, circuit of figure 5. channel 1?wrgd, channel 2? out , channel 3?igh side mosfet v gs , channel 4?ow side mosfet v gs current limit, short circuit, and latch-off protection the adp3180 compares a programmable current limit set point to the voltage from the output of the current sense ampli er. the level of current limit is set with the resistor from the ilimit pin to ground. during normal operation, the voltage on ilimit is 3 v. the current through the external resistor is internally scaled to give a current limit threshold of 10.4 mv/?. if the differ- ence in voltage between csref and cscomp rises above the current limit threshold, the internal current limit ampli er will control the internal comp voltage to maintain the average out- put current at the limit. after the limit is reached, the 3 v pull-up on the delay pin is disconnected, and the external delay capacitor is discharged through the external resistor. a comparator monitors the delay v oltage and shuts off the controller when the voltage drops below 1.8 v. the current limit la tch-off delay time is therefore set by the rc time constant discharging from 3 v to 1.8 v. the application information section discusses the selection of c dly and r dly . because the controller continues to cycle the phases dur- ing the latch-off delay time, if the short is removed before the 1.8 v threshold is reached, the controller will return to normal operation. the recovery characteristic depends on the state of pwrgd. if the output voltage is within the pwrgd window, the controller resumes normal operation. however, if a short circuit has caused the output voltage to drop below the pwrgd threshold, a soft-start cycle is initiated. the latch-off function can be reset either by removing and reap- plying vcc to the adp3180 or by pulling the en pin low for a short time. to disable the short circuit latch-off function, the external resistor to ground should be left open, and a high value (>1 m w ) d . d , . . . figure 2. overcurrent latch-off waveforms, circuit of figure 4. channel 1?wrgd, channel 2? out , channel 3?scomp pin of adp3180, channel 4?igh side mosfet vgs during startup when the output voltage is below 200 mv, a secondary current limit is active. this is necessary because the v oltage swing of cscomp cannot go below ground. this sec- ondary current limit controls the internal comp voltage to the pwm comparators to 2 v. this will limit the voltage drop across the low side mosfets through the current balance circuitry. there is also an inherent per phase current limit that will protect individual phases in the case where one or more phases may stop functioning because of a faulty component. this limit is based on the maximum normal mode comp voltage. dynamic vid the adp3180 incorporates the ability to dynamically change the vid input while the controller is running. this allows the output v oltage to change while the supply is running and supplying cur- rent to the load. this is commonly referred to as vid on-the- y (otf). a vid otf can occur under either light load or heavy load conditions. the processor signals the controller by changing the vid inputs in multiple steps from the start code to the nish code. this change can be either positive or negative. when a vid input changes state, the adp3180 detects the change and ignores the dac inputs for a minimum of 400 ns. this time is to prevent a false code due to logic skew while the rev. 0 adp3180 ?10? six vid inputs are changing. additionally, the t r st vid change initiates the pwrgd and crowbar blanking functions for a minimum of 250 s to prevent a false pwrgd or crowbar event. each vid change will reset the internal timer. figure 3 shows vid on-the-? y performance when the output voltage is stepping up and the output current is switching between mini- mum and maximum values, which is the worst-case situation. figure 3. vid on-the-fly waveforms, circuit of figure 5. vid change = 5 mv, 5 ? per step, 50 steps, i out change = 5 a to 65 a po w er good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits speci ed in the speci cations table based on the vid voltage setting. pwrgd will go low if the output voltage is outside of this speci ed range. pwrgd is blanked during a vid otf event for a period of 250 ? to prevent false signals during the time the output is changing. output crowbar as part of the protection for the load and output components of the supply, the pwm outputs will be driven low (turning on the low side mosfets) when the output voltage exceeds the upper po w er good threshold. this crowbar action will stop once the output voltage has fallen below the release threshold of approxi- mately 450 mv. tu r ning on the low side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvolt- age is due to a short of the high side mosfet, this action will current limit the input supply or blow its fuse, protecting the microprocessor from destruction. output enable and uvlo the input supply (vcc) to the controller must be higher than the uvlo threshold and the en pin must be higher than its logic threshold for the adp3180 to begin switching. if uvlo is less than the threshold or the en pin is a logic low, the adp3180 is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and holds the ilimit pin at g round. in the application circuit, the ilimit pin should be connected to the od pins of the adp3418 drivers. because ilimit is g rounded, this disables the drivers such that both drvh and drvl are grounded. this feature is important to prevent dis- charging of the output capacitors when the controller is shut off. if the driver outputs were not disabled, a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors. application information the design parameters for a typical intel vrd 10 compliant cpu application are as follows: ( ) = d ( d ) = . d (d) = . ( ) = . ( ) = . . w ( ) ( d ) = = . . = . ( ) = ( d ) = () = ( w ) = . adp3180 ?11? enable * see theory of operation section for description of optional r sw resistors power good r lim 200k c dly 39nf r t 249k r dly 390k r a 16.9k c fb 33pf c a 390pf c cs1 2.2nf r b 1.33k c b 1.5nf r ph1 124k from cpu r r 383k c cs2 1.5nf r cs1 35.7k r ph3 124k r sw1 * r sw3 * r sw2 * r cs2 73.2k r ph2 124k u1 adp3180 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit 3 1 4 5 2 6 10 14 7 8 9 11 12 13 26 25 24 28 27 19 22 21 20 23 15 18 17 16 c19 1 f r4 10 c20 33 f q8 ipd06n03l l4 600nh/1.6m bst in od vcc drvh sw pgnd drvl c15 4.7 f c18 4.7nf r3 2.2 r th 100k , 5% q9 ipd06n03l 1 2 3 8 7 6 45 u4 adp3418 d4 1n4148ws c17 4.7 f q7 ipd12n03l c16 100nf q5 ipd06n03l c12 100nf u3 adp3418 bst in od vcc drvh sw pgnd drvl c11 4.7 f d3 1n4148ws c14 4.7nf r2 2.2 q6 ipd06n03l 1 2 3 8 7 6 4 5 q2 ipd06n03l q3 ipd06n03l q4 ipd12n03l l3 600nh/1.6m c7 4.7 f c13 4.7 f 10 f 23mlcc around socket v cc(core) 0.8375v?1.6v 65a avg, 74a p k v cc(core) rtn 820 f/2.5v 8 fujitsu re series 8m esr (each) l2 600nh/1.6m c21 c28 c10 4.7nf r1 2.2 q1 ipd12n03l d2 1n4148ws c8 100nf c9 4.7 f u2 adp3418 1 2 3 8 7 6 45 bst in od vcc drvh sw pgnd drvl d1 1n4148ws v in 12v v in rtn l1 1.6 h c1 c6 470 f/16v 6 nichicon pw series ++ ++ + figure 4. 65 a intel pentium 4 cpu supply circuit, vrd 10 design rev. 0 adp3180 ?12? setting the clock frequency the adp3180 uses a t x ed-frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. with n = 3 for three phases, a clock frequency of 800 khz sets the switching frequency of each phase, f sw , to 267 khz, which represents a practical trade-off between the switching losses and the sizes of the output t lter components. tpc 1 shows that to achieve an 800 khz oscillator frequency, the correct value for r t is 249 k w . , r t can be calculated using: r nf pf m t sw = () ? . . ? () . pf and 1.5 m w . , . d d , . c dly for the soft-start ramp. this ramp is generated with a 20 a internal current source. the value of r dly will have a second order impact on the soft-start time because it sinks part of the current source to ground. however, as long as r dly is kept greater than 200 k w , . c dly can be approximated using: ca v r t v dly vid dly ss vid =? ? ? ? ? ? ? () t ss is the desired soft-start time. assuming an r dly of 390 k w , c dly is 36 nf. the closest standard value for c dly is 39 nf. once c dly has been chosen, r dly can be calculated for the current limit latch-off time using: r t c dly delay dly = . () r dly is less than 200 k w , c dly , or a longer latch-off time should be used. in no case should r dly be less than 200 k w . , r dly = 402 k w . w. . , , , , . , . , . , , . i vd fl r vid sw = ? () () l vr nd fv vid o sw ripple ? () () () l vm khz mv nh ? () = .. . ? , . . . . . . . . d, . d , . d ( ). , d . w . d d , . d . d ( ) . . . (.., , . ) (.., ). , . , , , , , . . , magnetics design references d (..) designing magnetic components for high-frequency dc-dc converters , by william t. mclyman, kg magnetics, inc. isbn 1883107008 rev. 0 adp3180 ?13? selecting a standard inductor the companies listed below can provide design consultation and deliver power inductors optimized for high power applications upon request. po w er inductor manufacturers () .. () .. () .. () .. d . ( ). . r ph(x) (summers), and r cs and c cs (t lter). the output resistance of the regulator is set by the following equations, where r l is the dcr of the output inductors: r r r r o cs ph x l = () () c l rr cs lcs = () r cs or r ph(x) . it is best to select r cs equal to 100 k w , r ph(x) by rear- ranging equation 6. r r r r r m m kk ph x l o cs ph x () () = == . . ? ? ?? , c cs : c nh mk nf cs = = . . ?? c cs in the layout so standard v alues can be used in parallel to get as close to the value desired. f or this example, choosing c cs to be a 1.5 nf and 2.2 nf in parallel is a good choice. for best accuracy, c cs should be a 5% or 10% npo capacitor. the closest standard 1% value for r ph(x) is 124 k w . d w d d, . , () .. , d. d , ( ) . d w d d . d w w w d w d figure 5. temperature compensation circuit values the following procedure and expressions will yield values to use for r cs1 , r cs2 , and r th (the thermistor value at 25?) for a given r cs value. 1. select an ntc to be used based on type and value. since we do not have a value yet, start with a thermistor with a va lue close to r cs . the ntc should also have an initial tolerance of better than 5%. 2. based on the type of ntc, nd its relative resistance value at two temperatures. the temperatures that work well are 50? and 90?. we will call these resistance values a (r th(50?) /r th(25?) ) and b (r th(90?) /r th(25?) ). note that the ntc s relative value is always 1 at 25?. 3. find the relative value of r cs required for each of these temperatures. this is based on the percentage change need- ed, which we will initially make 0.39%/?. we will call these r 1 (1/(1+ tc (t 1 e 25))) and r 2 (1/(1 + tc (t 2 e 25))), where tc = 0.0039, t 1 = 50?c and t 2 = 90?c. 4. compute the relative values for r cs1 , r cs2 , and r th using: r ab r r a b r b a r abrb arab r a r a rr r rr cs cs cs cs th cs cs 2 12 2 1 12 1 21 2 21 11 11 1 1 1 1 1 1 1 = ? () ? ? () +? () ? () ? ? () ? ? () = ? () ? ? ? = ? ? () . adp3180 ?14? 5. calculate r th = r th r cs , then select the closest value of thermistor available. also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k r r th actual th calculated = () () () . , r cs1 and r cs2 using equation 10: rrkr rr kkr cs cs cs cs cs cs 11 22 1 = =? () + () () () , r cs has been chosen to be 100 k w , w . , nths0603n01n1003jr ntc thermistor with a = 0.3602 and b = 0.09174. from these we compute r cs1 = 0.3796, r cs2 = 0.7195 and r th = 1.0751. solving for r th yields 107.51 k w , w , k = 0.9302. finally, we t nd r cs1 and r cs2 to be 35.3 k w . w . . w . w . d . ( i fb ) and ? ow- ing through r b . the value of r b can be found using equation 11: r vv i r vv a k b vid onl fb b = ? = ? = .. . ? () . w . . . . . . , . . , . ( c z ). next, there is an upper limit imposed on the total amount of bulk capacitance ( c x ) when one considers the vid on-the-? y voltage stepping of the output (voltage step v v in time t v with error of v err ) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step d i o : c li nr v c xmin o o vid z () ? ? ? ? ? ? ? ? () c l nk r v v t v v nkr l c k v v xmax o v vid v vid v o z verr v () + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? =? ? ? ? ? ? ? ln (13) to meet the conditions of these expressions and transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is larger than c x(max) , the system will not meet the vid on-the-? y speci- t cation and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). f or our example, 23 10 f 1206 mlc capacitors (c z = 230 f) we re used. the vid on-the-? y step change is 250 mv in 150 s with a setting error of 2.5 mv. solving for the bulk capacitance yields: c nh a mv fmf c nh mv mv sv m mv nh x min x max () () ? ? ? ? ? ? ? = + ? ? ? ? .. . .(. ). ... ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = f mf k . . where using eight 820 ? a1-polys with a typical esr of 8 m w, = . = . w. ( ) . lcr lfm ph xzo x ? ? = (. ) ? () , l x is 375 ph for the eight a1-polys capacitors, which satist es this limitation. if the l x of the chosen bulk capaci- tor bank is too large, the number of capacitors must be increased. one should note for this multimode control technique, all ceramic designs can be used as long as the conditions of equations 11, 12, and 13 are satist ed. po w er mosfets f or this example, the n-channel power mosfets have been selected for one high side switch and two low side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . the minimum gate drive v oltage (the supply voltage to the adp3418) dictates whether standard threshold or logic-level threshold mosfets must be used. with v gate ~10 v, logic-level threshold mosfets (v gs(th) < 2.5 v) are recommended. the maximum output current i o determines the r ds(on) requirement for the low side (synchronous) mosfets. with the adp3180, currents are balanced between phases, thus the current in each low side mosfet is the output current divided by the total number of mosfets ( n sf ). with conduction losses rev. 0 adp3180 ?15? being dominant, the following expression shows the total power being dissipated in each synchronous mosfet in terms of the ripple current per phase ( i r ) and average total output cur- rent ( i o ); pd i n ni n r sf o sf r sf ds sf =? () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () , d() . d , w. w . , ( ), d() ( ) . w . d() , . , w , . w . . ( ) . , ( d). w w w , . , . () . . , , n mf is the total number of main mosfets: pf vi n r n n c smf sw cc o mf g mf iss () = () , r g is the total gate resistance (2 w d w , r g = 3 w ) c iss is the input capacitance of the main mos- fet. it is interesting to note that adding more main mosfets ( n mf ) does not really help the switching loss per mosfet since the additional gate capacitance slows down switching. the best thing to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the fol- lowing, where r ds(mf) is the on resistance of the mosfet: pd i n ni n r cmf o mf r mf ds mf () () = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? () , , ( ) , . ( . w d) . , d ( = ), = () d() = w ( = ) d ( = ), = () d() = . w ( = ). , . = = . w . w . . . , q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet: p f n nq nq i v drv sw mf gmf sf gsf cc cc = + () + ? ? ? ? ? ? ( i cc times the v cc ) for the driver. for the adp3418, the maximum dissipation should be less than 400 mw. for our example, with i cc = 7 ma, q gmf = 22.8 nc, and q gsf = 34.3 nc, we t nd 260 mw in each driver, which is below the 400 mw dissipation limit. see the adp3418 data sheet for more details. ramp resistor selection the ramp resistor ( r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. the following expression is used for determining the optimum value: r al ar c r nh mpf k r r ddsr r = = = . . ? ? () a r is the internal ramp amplit er gain, a d is the current balancing amplit er gain, r ds is the total low side mosfet on resistance, and c r is the internal ramp capacitor value. the clos- est standard 1% resistor value is 383 k w . v adv rc f v v kpf khz v r r vid rrsw r = ? () = ? () = ... . ? () . , , . , , . , , . () . adp3180 ?16? comp pin ramp there is a ramp signal on the comp pin due to the droop volt- age and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input. v v nd nf c r rt r sw x o = ? ? () ? ? ? ? ? ? () , . . , r lim . the current limit threshold for the adp3180 is set with a 3 v source ( v lim ) across r lim with a gain of 10.4 mv/a ( a lim ). r lim can be found using the following: r av ir lim lim lim lim o = () r lim greater than 500 k w , , r lim may be needed. here, i lim is the average current limit for the output of the sup- ply. for our example, choosing 120 a for i lim , we t nd r lim to be 200 k w , w . i vvv ar i phlim comp max r bias d ds max r ? ?? ? () () () d, ( v comp(max) ) is 3.3 v, the comp pin bias voltage ( v bias ) is 1.2 v, and the cur- rent balancing amplit er gain ( a d ) is 5. using v r of 0.63 v and r ds(max) of 4.2 m w ( ), . v r . but make sure not to set the per phase limit lower than the average per phase current (i lim /n). there is also a per phase initial duty cycle limit determined by: dd vv v max comp max bias rt = ? () () , .. d d . , , ( ). w , . w d, . ( ) . . ( d ). rnrar rv v lndv nc r v rm m mv v nh v mf eodds lrt vid rt xo vid e = + + + ? () = + + + ? () .. .. . .. .. ?? ? m mv m ? ? = . . (25) tc rr l r rr r mf m m ph m mm m s ax o x o o x = ? () + ? =? () + ? = ... . .. . . ?? ? ?? ? () trrrc m mm mf s bx ox =+? () = + ? () = ..... ??? () t vl ar f vr vnh m khz vm s c rt dds sw vid e = ? ? ? ? ? ? ? = ? ? ? ? ? ? ? = . . .. . ? ? () t ccr crrcr mf f m mf m m f m ns d xzo xo zo = ? () + = ? () + = .(.) ... . ? ?? ? () , d, r ' is the pcb resistance from the b ulk capacitors to the ceramics and where r ds is the total low side mosfet on resistance per phase. for this example, a d is 5, v rt equals 0.63 v, r ' is approximately 0.6 m w ( ), l x is 375 ph for the eight al-poly capacitors. the compensation values can then be solved using the following: c nr t rr c ms mk pf a oa eb a = = = .. .. ? ?? () . adp3180 ?17? r t c s pf k a c a == = . . ? () c t r s k n b b b == = . . f ? . () c t r ns k p fb d a == = . f ? . () c a = 390 pf, r a = 16.9 k w , c b = 1.5 nf, and c fb = 33 pf. figure 6 shows the typical transient response using the compen- sation values. figure 6. typical transient response for design example c in selection and input current di/dt reduction in continuous inductor-current mode, the source current of the high side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude of one-nth of the maximum output current. to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: idi nd ia a crms o crms = ? = ?= . . . (34) note that the capacitor manufacturer?s ripple current ratings are often based on only 2,000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may be placed in parallel to meet size or height requirements in the design. in this example, the input capacitor bank is formed by three 2200 f, 16 v nichicon capacitors with a ripple current rating of 3.5 a each. to reduce the input-current di/dt to below the recommended maximum of 0.1 a/s, an additional small inductor (l > 1 h @ 15 a) should be inserted between the converter and the supply bu s. that inductor also acts as a t lter between the converter and the primary power source. rr vv vv cs new cs old nl flcold nl flhot 22 () () = ? () ? () () figure 7. ef ciency of the circuit of figure 4 vs. output current tuning procedure for the adp3180 1. build circuit based on compensation values computed from design spreadsheet. 2. hook up dc load to circuit, turn on and verify operation. also check for jitter at no-load and full-load. dc loadline setting 3. measure output voltage at no-load (v nl ). verify it is within tolerance. 4. measure output voltage at full-load cold (v flcold ). let board set for ~10 minutes at full-load and measure output (v flhot ). if there is a change of more than a couple of mil- livolts, adjust r cs1 and r cs2 using equations 35 and 37. 5. repeat step 4 until cold and hot voltage measurements remain the same. 6. measure output voltage from no-load to full-load using 5 a steps. compute the loadline slope for each change and then av erage to get overall loadline slope ( r omeas ). 7. if r omeas is off from r o by more than 0.05 m w , r ph values: rr r r ph new ph old omeas o () () = () . . . , , , , . r rr rr r r rr r cs new cs old th c cs old th c cs old cs new cs old th c th c 2 125 12522 125 25 1 1 () () () () () () () () () () = + + ? () ? () ? () . adp3180 ?18? 10. measure output ripple at no-load and full-load with scope and make sure it is within spec. ac loadline setting 11. remove dc load from circuit and hook up dynamic load. 12. hook up scope to output voltage and set to dc coupling with time scale at 100 ?/div. 13. set dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 14. measure output waveform (may have to use dc offset on scope to see waveform). try to use vertical scale of 100 mv/div or ner. 15. you will see a waveform that looks something like figure 8. use the horizontal cursors to measure v acdrp and v dcdrp as shown. do not measure the undershoot or overshoot that happens immediately after the step. v acdrp v dcdrp figure 8. ac loadline waveform 16. if the v acdrp and v dcdrp are different by more than a couple of millivolts, use equation 38 to adjust c cs . y ou may need to parallel different values to get the right one since there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this). cc v v cs new cs old acdrp dcdrp () () = (38) 17. repeat steps 11 to 13 and repeat adjustments if necessary. once complete, do not change c cs for the rest of the procedure. 18. set dynamic load step to maximum step size (do not use a step size larger than needed) and verify that the output wave- form is square (which means v acdrp and v dcdrp are equal). note: make sure load step slew rate and turn-on are set for a slew rate of ~150?50 a/? (for example, a load step of 50 a should take 200 ns?00 ns) with no overshoot. some dynamic loads will have an excessive turn-on overshoot if a minimum current is not set properly (this is an issue if using a vtt tool). initial transient setting 19. with dynamic load still set at maximum step size, expand scope time scale to see 2 ?/div to 5 ?/div. you will see a wave- form that may have two overshoots and one minor undershoot (see figure 9). here, v droop is the nal desired value. v droop v tran1 v tran2 figure 9. transient setting waveform 20. if both overshoots are larger than desired, try making the following adjustments in this order. (note: if these adjust- ments do not change the response, you are limited by the output decoupling.) check the output response each time y ou make a change as well as the switching nodes (to make sure it is still stable). a. make ramp resistor larger by 25% (r ramp ). b. for v tran1 , increase c b or increase switching frequency. c. for v tran2 , increase r a and decrease c a by 25%. 21. for load release (see figure 10), if v tranrel is larger than v tran1 (see figure 9), you do not have enough output capacitance. you will either need more capacitance or to make the inductor values smaller (if you change inductors, y ou need to start the design over using the spreadsheet and this tuning procedure). v droop v tranrel figure 10. transient setting waveform since the adp3180 turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. thus, you do not have to add headroom for ripple, allowing your load release v tranrel to be larger than v tran1 by that amount and still be meeting spec. if v tran1 and v tranrel are less than the desired nal droop, this implies that capacitors can be removed. when removing capaci- tors, make sure to check the output ripple voltage as well to make sure it is still within spec. rev. 0 adp3180 ?19? layout and component placement the following guidelines are recommended for optimal perfor- mance of a switching regulator in a pc system. key layout issues are illustrated in figure 11. 12v connector input power plane thermistor output power plane cpu socket keep-out area keep-out area switch node planes keep-out area keep-out area figure 11. layout recommendations general recommendations , . , , , , . . w . w , . ( d) , . . d . . d . . . ( ) (.., ). , . , . (.., ) . . . , , . w (.., ) , , , . . . , . . , , . , . , . , . . . . . c03532?0?2/03(0) printed in u.s.a. ?20? adp3180 outline dimensions 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ae coplanarity 0.10 rev. 0 |
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